A semiconductor manufacturing process forms one or more patterns on or in a substrate to form a semiconductor device. For example, photolithography transfers a pattern from a mask to photoresist on the substrate, thereby resulting in a photoresist pattern which serves as a template for subsequent material addition or removal steps in the formation of the semiconductor device. Because of variations in the semiconductor manufacturing process, the resulting pattern on/in the substrate may not always correspond sufficiently to the desired pattern. Variations in the resulting pattern may adversely affect device performance, especially when alignment and/or spacing between sub-millimeter scale features is important. For quality control purposes, feature sizes of a pattern are measured after forming of the pattern on/in the substrate to verify that the pattern satisfies desired tolerances. Such size measurements include, for example, measuring a width of a line pattern or a diameter of a hole pattern.
In order to evaluate size information of the formed patterns, images of the patterns after formation may be analyzed, for example, by extracting edges of the patterns and measuring a dimension of the pattern based on the extracted edges. When manufacturing semiconductor devices having small feature sizes (e.g., less than 1 μm), the images may be obtained using an imaging device sufficiently powerful to resolve the individual features of the pattern. For example, a scanning electron microscope (SEM) is used to obtain plan view images of the formed patterns.
For larger size features, the size measurements may focus on determining a dimension (e.g., width, length, diameter, etc.) of the formed pattern. Variations and/or roughness along the edge of the pattern may thus be trivial compared to the overall dimension of the pattern. For example, a 10-nm edge roughness for a 100-μm wide line pattern may be a relatively insignificant deviation. However, as feature sizes decrease, even minute variations introduced by edge surface roughness may result in a significant deviation in ideal device performance. For example, a 10-nm edge roughness for a 50-nm diameter hole pattern may be a relatively significant deviation. The measurement of formed patterns may thus include a measurement of edge roughness as well as pattern dimension. When applied to hole or dot patterns, the edge roughness is termed hole edge roughness. When applied to a small contact hole or dot patterns (e.g., with feature sizes less than 50 nm), the edge roughness is termed contact edge roughness (CER).